1. Field of the Invention
The invention relates generally to first in first out (FIFO) memory and registers, and more specifically to FIFO control in a multiprocessor system passing data with a shared FIFO.
2. Background Information
First-in first-out memory devices are well known. In some cases they may be formed out of a parallel array of registers or flip-flops coupled in series together or a register file with a read pointer (i.e., pop pointer) and a write pointer (i.e., push pointer). In another case, the FIFO memory device may be a may be a random access memory (RAM) array with a read pointer (i.e., pop pointer) and a write pointer (i.e., push pointer).
A FIFO memory may be used to buffer data between two digital devices operating at different speeds. FIFO memory devices are often used to buffer data such as in the case of a universal asynchronous receiver transmitter (UART) or a video frame buffer. In these cases, the data is written into the FIFO memory and retrieved from the FIFO memory in the same order. However, the data may be clocked into the FIFO memory at one rate and read out from the FIFO memory at another rate. In this case, the FIFO memory can be considered to be asynchronously clocked. If data is clocked into and out of the FIFO memory at the same rate, the FIFO memory can be considered to be synchronously clocked.
The storage devices generally used in FIFO memory are static type memory cells in order that the cells do not need refreshing and that they do not constantly need to be clocked. Examples of these types of memory cells are a latch or a flip-flop.
Basic control of FIFO memories devices is known, such as how to control the pushing of data (i.e., write) into a FIFO memory and how to pop data out (i.e., read) from a FIFO memory, as well as providing status information to indicate whether or not a FIFO memory is full or empty.